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data sheet 1 rev. 1.0 www.infineon.com 2016-09-29 TLE9202ED dual 6 a h-bridge with spi overview features ?r dson of 100 mw per switch typ. at tj = 25 o c ? logic inputs 3.3 ? v and 5.0 ? v ttl / cmos-compatible ?low standby current ? chopper current limitation ? short circuit shut down with latch behavior ? overtemperature shut down with latch behavior ?v s undervoltage shutdown ? open load detection in on and off state ? detailed spi diagnosis or simple error flag ? green product (rohs compliant) ? aec qualified description the TLE9202ED contains two in dependent gene ral purpose 6 ? a h-bridges in one package. it is designed for (but not limited to) the control of dc motors or other inductive loads in automotive applications. the outputs can be pulse width modulated at frequencies up to 20 khz. pwm/dir control reduces the number of pwm capable pins needed on the microcontroller side. for load currents above the current limitation threshold (8 a typ.) the h-bridge goes into chopper current limitation mode. it is protected a gainst short circuits and overtemperature and prov ides extensive diagnosis via spi or basic error feedback via erro r flag. open load can be detected when the bridge is disabled or during pwm operation of inductive loads. type package marking TLE9202ED pg-dso-36-72 TLE9202ED
data sheet 2 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi 1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 output stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5 current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 short circuit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7 short circuit to battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.8 short circuit over load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.9 overtemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.10 undervoltage shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.11 open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.11.1 open load detection in off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.11.2 open load detection in on state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.12 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.12.1 error flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.12.2 spi register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.12.2.1 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.12.2.2 diagnosis register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.12.2.3 revision register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table of contents
data sheet 3 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi pin configuration 1 pin configuration 1.1 pin assignment figure 1 pin configuration TLE9202ED 1.2 pin definitions and functions table 1 pin defintions and functions pin symbol description 1gnd 1) ground 2 out2_1 output 2 of h-bridge 1. connect to pin 3 3 out2_1 output 2 of h-bridge 1. connect to pin 2 4 vs_1 supply voltage of h-bridge 1. connect to pin 33 5 si_1 spi serial input of h-bridge 1 6 csn_1 spi chip select (low active) of h-bridge 1 7 sck_1 spi clock input of h-bridge 1 8nc not connected 9 dis_2 disable. disables the output (all mosfets off) of h-bridge 2 10 pwm_2 pulse width modulation input of h-bridge 2 11 dir_2 direction input to define direct ion of the motor current of h-bridge 2 12 vso_2 supply pin for so output of h-bridge 2 connect to 5 v or 3.3 v depending on desired logic level 13 so_2 spi serial output of h-bridge 2 14 nc not connected 15 vs_2 supply voltage of h-bridge 2. connect to pin 22 16 out1_2 output 1 of h-bridge 2. connect to pin 17 gnd out1_1 out1_1 vs_1 nc so_1 vso_1 dir_1 pwm_1 dis_1 nc sck_2 csn_2 si_2 vs_2 out2_2 out2_2 gnd gnd out2_1 out2_1 vs_1 si_1 csn_1 sck1 nc dis_2 pwm_2 dir_2 vso_2 so_2 nc vs_2 out1_2 out1_2 gnd 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
data sheet 4 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi pin configuration 17 out1_2 output 1 of h-bridge 2. connect to pin 16 18 gnd 1) ground 19 gnd 1) ground 20 out2_2 output 2 of h-bridge 2. connect to pin 21 21 out2_2 output 2 of h-bridge 2. connect to pin 20 22 vs_2 supply voltage of h-bridge 2. connect to pin 15 23 si_2 spi serial input of h-bridge 2 24 csn_2 spi chip select (low active) of h-bridge 2 25 sck_2 spi clock input of h-bridge 2 26 nc not connected 27 dis_1 disable. disables the output (all mosfets off) of h-bridge 1 28 pwm_1 pulse width modulation input of h-bridge 1 29 dir_1 direction input to define direct ion of the motor current of h-bridge 1 30 vso_1 supply pin for so output of h-bridge 1. connect to 5 v or 3.3 v depending on desired logic level 31 so_1 spi serial output of h-bridge 1 32 nc not connected 33 vs_1 supply voltage of h-bridge 1, connect to pin 4 34 out1_1 output 1 of h-bridge 1. connect to pin 35 35 out1_1 output 1 of h-bridge 1. connect to pin 34 36 gnd 1) ground 1) all ground pins (gnd) have to be connected via a low ohmic, low inductive connection (e.g. a ground plane) table 1 pin defintions and functions pin symbol description
data sheet 5 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi pin configuration 1.3 terms please note: for the sake of simplicity all followin g diagrams and parameters ar e describing one single h- bridge only. to distuinguish between the two h-bridge s according to the pin assignment, the index ?_1? has to be added for h-bridge 1 and index ?_2? has to be added for h-bridge 2. figure 2 terms TLE9202ED (single h-bridge) csn pwm so vso dis dir out1 gnd vs out2 v vso i so i pw m i dir i dis i vso v so v pw m v dir v dis v sc k i out1 i out2 v out2 v out1 i vs v vs sck si i si v si i sc k i csn v csn
data sheet 6 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi block diagram 2 block diagram figure 3 block diagra m (single h-bridge) csn sck pw m vso dis dir out1 gnd vs out2 contr ol logic gate driver current monitor internal supply charge pump tem per atur e monitor si so
data sheet 7 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi block description 3 block description 3.1 power supply all internal supply voltages are derived from the pin vs . a charge pump provides the gate voltage for the high side switches. the charge pump does not require an external capacitor. the output buffer of the digital output so is supplied by the pin vso. therefore the output level at so can be easily configured for 3.3 v or 5 v logic by connecting vso to th e respective voltage. 3.2 sleep mode in order to minimize current consumption during inac tive phases the device can be put into sleep mode by pulling the vso pin to gnd. this func tionality can also be used to provid e a second switch off path for the outputs similar to an enable pin, simply by dr iving vso directly from a microcontroller output. since vso is supplying also the output buffer of the so signal it has to be ensured that the microcontroller output can provide sufficient current. alternatively an external mosfet or a driver stage could be used to switch the vso supply voltage. to account for dynamic switching currents it might be advisable to buffer vso with a small capacitor (see figure 13 ?application example vso as enable input? on page 25 ). please note that the push pull stage of the so output provides a current re turn path to vso via the bulk diode of the highside mosfet. therefore it has to be ensured that the voltage at so never exceeds the voltage at vso by more than 0.3 v. figure 4 so output buffer vso so spi_serial_ out sleep_mode v_vso_sleep + -
data sheet 8 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi block description 3.3 output stages the output stages consist of four n-channel mosfets in h-bridge config uration. the outputs are protected against short circuits and over temperature. the bridge is controlled using the inpu ts pwm and dir. the signal at dir is defining the direction of the driven dc motor whereas the pwm sign al sets the duty cycle. the outputs can be set tristate (i.e. high side and low side switches are turned off) by setting dis to high level. figure 5 operation modes table 2 output truth table dis pwm dir out1 out2 comment 1 x x z z disabled, outputs tristate 01 1 h l forward / clockwise 0 1 0 l h reverse / counterclockwise 0 0 1 h z freewheeling in hs (forward) 0 0 0 z h freewheeling in hs (reverse) dir = 1, pwm =1 forward dir =1, pwm = 0 freewheeling through hs 2 body diode (forward) dir = 0, pwm = 1 reverse dir = 0, pwm =1 freewheeling through hs 1 body diode (reverse) hs2 on ls1 on m i l hs1 off ls2 off ls2 on hs2 off hs1 on ls1 off m i l ls2 off hs2 off hs1 on ls1 off m i l ls2 off hs2 on hs1 off ls1 off m i l
data sheet 9 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi block description 3.4 protection and diagnostics both output stages of the TLE9202ED are eq uipped with fault diagnostic functions: ? short to battery voltage (scb) ? short to ground (scg) ?open load (ol) ? over-temperature (ot) 3.5 current limitation to limit the output current a chopper current limita tion is integrated. curren t measurement for current limitation is done in the high side path. figure 6 chopper current limitation figure 6 shows the behavior of th e current limitation for over current de tection in hs1. it applies accordingly also for hs2. when the current in high-side switch of out1 (hs1) exceeds the limit i l longer than the blanking time t b , the low side switch of out2 (ls2) is switched off, in dependent of the input signal at pwm. this leads to freewheeling through the bulk diode of hs2 and therefore to a decrease of the load current. as soon as the current falls below i l , out2 is switched back to normal operation, i.e. the outputs follow the inputs according to the truth table. to avoid high switching frequenc ies in case of low induct ive loads the minimum time between two transitions is limited to t trans . i out time i l t trans t b hs1 m ls 1 hs2 ls2
data sheet 10 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi block description 3.6 short circuit detection figure 7 short to ground detection the short circuit to ground detection is activated when the current through one of the high side switches rises over the threshold i sc and remains higher than i sc for at least the filter time t sdf within the blanking time t b . both outputs will be switched off and the failure will be re ported in the spi diagnosis register. the outputs can be re-activated by disabling and enabling the bridge via th e disable signal dis, pulling vso to gnd or by a reset command via spi. 3.7 short circuit to battery a short circuit to battery is detected in the same way as a short circuit to ground, only in the low side switch instead of the high side switch. 3.8 short circuit over load short circuit over load will trigger the short circuit dete ction either of the high side or the low side switch (whichever is faster). 3.9 overtemperature in case of high dc-currents, insuff icient cooling or high ambient temper ature, the chip temperature may rise above the thermal shut-down temperature t jsd . in that case, all output transistors are turned off. overtemperature shutdown is latching. the outputs can be re-activated as soon as the junction temperature has fallen below the switch-on temperature t jso . i out i l time t b i sc pwm t sdf t < t b out1 current both outputs off current tracking current limitation, freewheeling in hs short dir tristate out2 tristate tristate short circuit detected
data sheet 11 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi block description 3.10 undervoltage shut-down if the supply voltage at the vs pins fall s below the undervoltage detection threshold v uv_off , the outputs are turned off. the undervoltage detection is not latching. that means that as soon as v s rises above v uv_on again, the device is returning to normal operation. 3.11 open load detection 3.11.1 open load detection in off state when the bridge is disabl ed (dis = high) the open load in off detection becomes active. two diagnostic current sources will then be connected to the outputs, a pull up current source at out1 and a pull down current source at out2. the pull down current source is stronger than the pull up cu rrent source and therefore will pull down out1 if a load is present. if no load is present out1 will be pulled high by the pull up current source. this is detected by a comparator and reported in the spi diagnosis register. please note that capacitors that might be placed at th e outputs for emc reasons first have to be discharged by the pull down current source at out2 for th e open load detection to work properly. also, if current is flowing through the load at the time of disabling the freewheel ing current will force the outputs towards supply voltage v s . this may lead to an erroneous reporting of open load. therefore the first diagnostic readin g after disabling should be discar ded and a second reading should be taken after the load is deenergized and the ou tput capacitors are discharged completely. the open load detection can be disabled by setting the oldis bit in the ctrl_reg register. this will disconnect the diagnostic current so urces and suppress the reporting of op en load in the dia_reg register. figure 8 open load detection in off state 3.11.2 open load detection in on state the TLE9202ED contains an open load diagnosis during operation for inductive load s. it evaluates whether freewheeling occurs in the switching pha se. in order to avoid inadvertent tr iggering of the open load diagnosis a failure counter is implemented. there have to be at leas t 5 occurances of the internal open load signal (i.e. 5 pwm pulses without freewheeling detected) before open load is reported in th e spi diagnosis register. depending on the operation conditions and on external ci rcuitry like the output capa citors it is possible that open load is indicated although the load is present. this might be the case for example during a direction change or for small load currents respectively small pwm duty cycles. therefore it is recommended to evaluate the open load diagnosis only in known suitable operating condit ions and to ignore it otherwise. the open load diagnosis is not latching. 5v int. + - v ref_ol out1 ol out2 m
data sheet 12 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi block description 3.12 serial peripheral interface (spi) for diagnosis purposes the TLE9202ED is equipped with a ?serial peripher al interfac e? (spi). the spi of several TLE9202EDs can be connected in daisy chain configuration in orde r to save microcontroller interface pins. both channels of the TLE9202ED is co nfigured as a ?slave? device. this means that the c as the master is providing the chip select (csn) and clock signal (sck). a data transfer on the spi bus is initiaded with a falling edge on csn and is terminated by a rising edge on csn. the data on the serial input pin si is sampled with the falling edge of sck, the serial data output at so is determined by the rising clock edge. the data is transferred ?msb first?. the word length of the spi is 8 bit. please note that there is no check fo r the number of clocks within a spi frame. any low pulse at csn will be regarded as one frame. 3.12.1 error flag between the falling edge of csn and the first rising edge of sck an ad ditional error flag signal is set asynchronously at the so pin. the error flag signal se t to high whenever the ou tput stages are shut down (tristate) due to a failure or due to disabling of the output stages. additionally the ef signal is or?ed with the si input signal. by connecting the so of one device to the si of the next device the ef signal can be routed through similar to a spi daisy chain configuration. this flag can be used for simple error feedback without spi communication by connecting sck and csn to gnd permanently (see figure 11 ?application example h-br idge with error flag? on page 23 ). figure 9 spi timing defini tion (drawing not to scale) 10 2 3 4 5 6 7 10 2 3 4 5 6 7 ef z z csn sck si so command n si: data will be accepted on the falling edge of sck -signal so: state will change on the rising edge of sck -signal answer to command n-1 10 9 2 1 3 8 5 6 7 ef 4
data sheet 13 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi block description 3.12.2 spi register description the TLE9202ED provides detailed diagnosis and the op tion to control the outp uts via spi. following commands are available (x = don?t care, d = data): the first spi response provided after power up is the device revision number (rd_rev). for any unspecified commands the device will respond with the co ntent of the diagnosis register (rd_dia). the registers are addressed wordwise. table 3 spi command set command input byte description rd_dia 000x xxxx read diagnosis register res_dia 1) 1) after a res_dia command, the device will respond with the diagnosis register value 100x xxxx reset diagnosis register rd_rev 001x xxxx read device revision number rd_ctrl 011x xxxx read control register wr_ctrl 111d dddd write control - sets and returns contro l register values wr_ctrl_rd_dia 110d dddd write control and read diagnosis- sets control register values and returns diagnosis register values
data sheet 14 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi block description 3.12.2.1 control register control register ctrl_reg control register reset value:00 h 76543210 cmd oldis sin sen sdir spwm rw rw rw rw rw rw field bits type description cmd 7:5 rw command 011: rd_ctrl 110: wr_ctrl_rd_dia 111: wr_ctrl oldis 4rw open load disconnect 1: open load current source disconnected. sin 3rw spi control 0: control outputs via pwm/dir inputs 1: control outputs via spi note: can only be set if dis=0 and pwm=0 and dir=0. any change of the dis, pwm or dir signals will reset this bit and revert to standard control via pwm/dir sen 2rw 1: enable outputs in case of spi control (sin=1) 0: disable outputs in case of spi control (sin=1) sdir 1rw dir signal in case of spi control (sin=1) spwm 0rw pwm signal in case of spi control (sin=1)
data sheet 15 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi block description 3.12.2.2 diagnosis register diagnosis register diagnosis truth table the short circuit and vs undervoltage diagnosis is coded in the dia bits according to the following truth table. together with transmission validation bit tv (always 0) it is ensured th at there is always at least one 1->0 change at so during a valid transmission. therefore a ?stuck at? failure of the so pin can be detected. dia_reg diagnosis register reset value:df h 76543210 en ot tv cl dia4 dia3 dia2 dia1 rrrrrrrr field bits type description en 7r 1 = outputs enabled by low signal on pin dis 0 = outputs disabled by high signal on pin dis ot 6r 0 = overtemperature shutdown tv 5r always 0 - used for tr ansmission validation cl 4r 0 = current limitation active dia4 3r diagnosis bit 4 dia3 2r diagnosis bit 3 dia2 1r diagnosis bit 2 dia1 0r diagnosis bit 1 table 4 encoding of diagnosis bits (sorted by hex value, only listed combinations are valid) type dia4 dia3 dia2 dia1 hex comment no failure 1 1 1 1 0xf - short to gnd at out1 (scg1) 1 1 1 0 0xe latched short to battery at out1 (scb1) 1 1 0 1 0xd latched open load (ol) 1 1 0 0 0xc not latched short to gnd at out2 (scg2) 1 0 1 1 0xb latched short to gnd at out1 and out2 (scg1, scg2) 1 0 1 0 0xa latched short to bat. at out1 and short to gn d at out2 (scb1, scg2) 1 0 0 1 0x9 latched short to battery at out2 (scb2) 0 1 1 1 0x7 latched short to gnd at out1 and short to bat. at out2 (scg1, scb2) 0 1 1 0 0x6 latched short to battery at out1 and ou t2 (scb1, scb2) 0 1 0 1 0x5 latched vs undervoltage (vs_uv) 0 0 1 1 0x3 not latched
data sheet 16 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi block description reset behavior of diagnosis register the diagnosis register is re set by the following events: a change of the dir signal will lead to a reset of current limitation (cl) or open load in on (ol) error messages. the open load in on failure will also be reset automati cally if the open load condit ion no longer persits, i.e. freewheeling is detected for five or more consecutive pulses. 3.12.2.3 revision register the revision register contains the device revision corresponding to the mask set. revision register table 5 diagnosis reset types name type comment por power on reset reset due to po wer up, undervoltage or sleep mode enr enable reset reset due to disabling/enabling of the outputs by dis pin or bit sen in ctrl_reg spir spi reset reset by sending the res_dia command via spi rev_reg revision register reset value:00 h 76543210 0010 rev rrrr r field bits type description 0 7r fixed to 0 0 6r fixed to 0 1 5r fixed to 1 0 4r fixed to 0 rev 3:0 r device revision corresponding to mask set
data sheet 17 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi general product characteristics 4 general product characteristics 4.1 absolute maximum ratings notes 1. stresses above the ones listed he re may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. integrated protection functions are designed to preven t ic destruction under fault conditions described in the data sheet. fault conditions are cons idered as ?outside? normal operatin g range. protection functions are not designed for continuous repetitive operation. table 6 absolute maximum ratings 1) t j = -40c to +150c; 1) not subject to production test, specified by design. parameter symbol values unit note or test condition number min. typ. max. junction temperature t j -40 150 ? 150 175 c ? 100 h cumulative p_5.1.1 storage temperature t s -55 ? 150 c ? p_5.1.2 ambient temperature t a -40 ? 125 c ? p_5.1.3 supply voltage v vs -0.3 ? 40 v ? p_5.1.4 supply for logic output v vso -0.3 ? 5.5 v ? p_5.1.5 voltage at logic inputs v in -0.3 ? 5.5 v ? p_5.1.6 voltage at logic output so v so -0.3 ? v vso +0.3 v both conditions must be observed p_5.1.7 -0.3 ? 5.5 esd susceptibility esd susceptibility to gnd acc. hbm v esd -2 ? 2 kv hbm 2) 2) esd susceptibility hbm according to eia/jesd22-a114-b (1.5 k ? , 100 pf) p_5.1.8 esd susceptibility to gnd acc. cdm v esd -500 ? 500 v cdm 3) 3) esd susceptibility, charged device model ?cdm? eia/jesd22-c101 p_5.1.9 esd susceptibility to gnd acc. cdm, corner pins v esd -750 ? 750 v cdm 3) , corner pins p_5.1.10
data sheet 18 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi general product characteristics 4.2 functional range note: within the functional or operatin g range, the ic operates as descri bed in the circuit description. the electrical characteristics are specified within the co nditions given in the el ectrical characteristics table. 4.3 thermal resistance note: this thermal data was generated in accord ance with jedec jesd51 standards. for more information, go to www.jedec.org . table 7 functional range 1) 1) not subject to production test, specified by design. parameter symbol values unit note or test condition numbe r min. typ. max. supply voltage range v s v uv_off ?28v? p_5.2.1 v s supply voltage slew rate dv s /dt -10 ? 10 v/s ? p_5.2.2 so buffer supply voltage v so 2.9 ? 5.5 v ? p_5.2.3 junction temperature t j -40 ? 150 c ? p_5.2.4 table 8 thermal resistance 1) 1) not subject to production test, specified by design. parameter symbol values unit note or test condition number min. typ. max. junction to case r thjc ? ? 1 k/w 0.5 w on each h-bridge p_5.3.1 junction to ambient r thja ?23?k/w0.5 w on each h-bridge 2) 2) specified r thja value is according to jedec jesd51-2,-5,-7 at na tural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 114.3 1.5 mm boar d with 2 inner copper layers (2 70 mm cu, 2 35 mm cu). where applicable a thermal via array under the exposed pad contacted the first inner copper layer. p_5.3.2
data sheet 19 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi electrical characteristics 5 electrical characteristics table 9 electrical characteristics v s =8v to 28v; v vso =2.9v to 5.5v; t j = -40c to +150c; positive cu rrent flowing according to figure 2 (unless otherwise specified) parameter symbol values unit note or test condition number min. typ. max. supply supply current i vs ??13ma f pwm = 2 khz; i out = 0 a; v vs = 13.5 v p_6.0.1 supply current sleep mode 25 c i vs ? 1930a v vs = 13.5 v ; v vso = 0 v ; v outx = 0 v; t j = 25 c p_6.0.2 supply current sleep mode 150 c 1) ??50a v vs = 13.5 v ; v vso = 0 v , v outx = 0 v; t j = 150 c p_6.0.3 vso sleep mode threshold v vso_sleep 0.5 ? 2.0 v ? p_6.0.4 vso input current, csn high i vso ? ? 100 a i so =0 a; v csn > 2 v p_6.0.5 vso input current, csn low i vso ??1.0ma i so =0 a ; v csn = 0 v p_6.0.6 vs undervoltage undervoltage at v s v uv_ off 3.5 4.2 5.0 v switch off threshold p_6.0.7 undervoltage at v s v uv_on 3.6 4.4 5.2 v switch on threshold p_6.0.8 undervoltage at v s v uv_hy 0.1 ? 0.2 v hysteresis p_6.0.9 vs undervoltage detection filter time 1) t uv ?1?s? p_6.0.10 inputs pwm,dir,sck,si low level v input_l ??0.8v? p_6.0.11 high level v input_h 2.0??v? p_6.0.12 hysteresis v input_hys 0.1 0.3 ? v ? p_6.0.13 pull down current i in_pd 9 3885a v in = 5.5 v p_6.0.14 input capacity 1) c in ??15pf v bias = 2v; v test = 20mvpp; f = 1 mhz p_6.0.15 inputs dis, csn low level v input_l ??0.8v? p_6.0.16 high level v input_h 2.0??v? p_6.0.17 hysteresis v input_hys 0.1 0.3 ? v ? p_6.0.18 pull up current i in_pu 9 3885a? p_6.0.19 input capacity 1) c in ??15pf v bias = 2 v; v test = 20 mvpp; f = 1 mhz p_6.0.20
data sheet 20 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi electrical characteristics output so low level v so_l 0.0 ? 0.4 v i so = -1 ma p_6.0.21 high level v so_h v vso - 0.75 ? v vso v i so = 1 ma, 2.9 v < v vso < 5.5 v p_6.0.22 tristage leakage current i so -5 ? 5 a 0v < v so < v vso ; v vso = 5.5 v p_6.0.23 output capacity 1) c so ??19pf v bias = 2 v; v test = 20 mvpp; f = 1 mhz p_6.0.24 power outputs out1, out2 on resistance low side r outl ? 100 ? m ? i out =2a; t j = 25 c p_6.0.25 ? ? 200 m ? i out =2a; t j = 150 c on resistance high side r outh ? 100 ? m ? i out =2a; t j = 25 c p_6.0.26 ? ? 200 m ? i out =2a; t j = 150 c leakage current i out1(off) i out2(off) -25 ? 25 a v vs = 13.5 v; outputs off; oldis high p_6.0.27 -100 25 v vs = 13.5 v; sleep mode free-wheel diode forward voltage u d ?0.91.0v i d = 2 a p_6.0.28 output switching times 2) rise time hs t r (hs) 5?40s v vs = 13.5 v; r load =6.8 ? p_6.0.29 fall time hs t f (hs) 5?40s p_6.0.30 rise time ls t r (ls) 1.0 ? 7.0 s p_6.0.31 fall time ls t f (ls) 1.0 ? 7.0 s p_6.0.32 pwm frequency 1) f pwm 0?20khz? p_6.0.33 output delay times 2) output on-delay hs t d_on(hs) ??80s v vs = 13.5 v; r load =6.8 ? p_6.0.34 output off-delay hs t d_off(hs) ??80s p_6.0.35 output on-delay ls t d_on(ls) ??10s p_6.0.36 output off-delay ls t d_off(ls) ??10s p_6.0.37 disable delay time t d_dis ??80s p_6.0.38 enable delay time t d_en ??80s p_6.0.39 disable/enable filter time 1) t f_en 0.4 ? 3 s p_6.0.40 wake up delay time 1) t wu ? ? 1 ms vso high --> out high p_6.0.41 table 9 electrical characteristics v s =8v to 28v; v vso =2.9v to 5.5v; t j = -40c to +150c; positive cu rrent flowing according to figure 2 (unless otherwise specified) parameter symbol values unit note or test condition number min. typ. max.
data sheet 21 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi electrical characteristics chopper current limitation current limit |i l | 6.0 8.0 10.0 a v vs = 13.5 v p_6.0.42 blanking time 1) t b 5813s? p_6.0.43 minimum transition time 1) t trans -95-s? p_6.0.44 short circuit detection short circuit detection threshold high side switch |i sc_h | 8.0 11.5 14.5 a v vs = 13.5 v p_6.0.45 short circuit detection threshold low side switch |i sc_l | 8.0 11.5 14.5 a p_6.0.46 current tracking high side |i sc_h |-| i l | 2.0 4.0 5.2 a p_6.0.47 current tracking low side |i sc_l |- | i l | 1.8 3.5 5.2 a p_6.0.48 short circuit detection filter time 1) t sdf -2-s- p_6.0.49 open load detection in off state pull up current at out1 i out1_ol 60 140 200 a v vs = 13.5 v; v out1 = 0 v p_6.0.50 pull down current at out2 i out2_ol -500 -350 -200 a v vs = v out2 = 13.5 v p_6.0.51 ratio of current sources ratio _ i ol 1.8 2.5 3.5 - - p_6.0.52 open load detection in off filter time 1) t f_ol 40--s- p_6.0.53 spi timing ( figure 9 ?spi timing definition (d rawing not to scale)? on page 12 ) 1) cycle-time (1) tcyc 490 - - ns referred to master p_6.0.54 enable lead time (2) tlead 50 - - ns referred to master p_6.0.55 enable lag time (3) tlag 150 - - ns referred to master p_6.0.56 data valid (4) 3) tv - - 150 ns cl = 200 pf referred to TLE9202ED p_6.0.57 - - 230 ns cl = 350 pf referred to TLE9202ED data setup time (5) tsu 40 - - ns referred to master p_6.0.58 data hold time (6) th 40 - - ns referred to master p_6.0.59 disable time (7) tdis - - 100 ns referred to TLE9202ED p_6.0.60 transfer delay (8) tdt 2 - - s referred to master p_6.0.61 disable lead time(9) tdld 250 - - ns referred to master p_6.0.62 disable lag time (10) tdlg 250 - - ns referred to master p_6.0.63 table 9 electrical characteristics v s =8v to 28v; v vso =2.9v to 5.5v; t j = -40c to +150c; positive cu rrent flowing according to figure 2 (unless otherwise specified) parameter symbol values unit note or test condition number min. typ. max.
data sheet 22 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi electrical characteristics thermal shutdown thermal shutdown junction temperature 1) t jsd 150 175 - o c- p_6.0.64 thermal switch-on junction temperature 1) t jso 125 - - o c p_6.0.65 1) not subject to production test, specified by design. 2) output switching times are measured be tween 20% and 80% of the output swing. 3) v so timing thresholds are 20% / 80% of v vso for 4.5 v < v vso < 5.5 v and 30% / 70% of v vso for 2.9 v < v vso < 4.5 v. table 9 electrical characteristics v s =8v to 28v; v vso =2.9v to 5.5v; t j = -40c to +150c; positive cu rrent flowing according to figure 2 (unless otherwise specified) parameter symbol values unit note or test condition number min. typ. max.
data sheet 23 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi application information 6 application information note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certai n functionality, condition or quality of the device. the function of the described circuits mu st be verified in the real application. figure 10 application example h-bridge with spi interface figure 11 application example h-bridge with error flag dis vso pwm dir out1 gnd v s out2 m vbat <33 nf <33 nf 100 nf 100 uf vs< 40 v so csn 3. 3 or 5v digital supply c sck si dis vso pwm dir out1 gnd v s out2 m vbat <33 nf <33 nf 100 nf 100 uf vs< 40 v so csn 3. 3 or 5v digital supply c sck si
data sheet 24 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi application information figure 12 spi daisy chain konfiguration (other signals omitted for clarity) c dis vso pw m dir out1 gnd v s out2 m <33 nf <33 nf so csn sck si dis vso pw m dir out1 gnd v s out2 m <33 nf <33 nf so csn sck si
data sheet 25 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi application information figure 13 application example vso as enable input figure 14 examples for re verse polarity protection the TLE9202ED is not protected against reverse polarity. external measures have to be taken to ensure the right polarity of the supply voltage. dis vso (en) pwm dir out1 gnd v s out2 m vbat <33 nf <33 nf 100nf 100uf vs< 40v so csn 3.3 or 5v digital supply c sck si 1nf 100 nf 100 f main relay ignition switch v s battery vs < 4 0v reverse polarity protection via main relay 100 nf 100 f v s battery vs < 40v reverse polarity protection using p -fet 10 v 10 k
data sheet 26 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi package outlines 7 package outlines figure 15 pg-dso-36-72 green product (rohs compliant) to meet the world-wide customer requirements for en vironmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb -free soldering according to ipc/jedec j-std-020). 0.08 c seating plane 0.08 a b c 36x standoff c index marking 18 coplanarity 36x 0.1 c a-b 2x 0.1 c d 2x d 0.2 c 1) 2.5max. 2.4 0.0 -0.2 0.1 0.1 0.5 0.25 0.06 17 x 0.5 = 8.5 0 . 1 8 + 0 . 0 9 8 m a x . 0.7 0 . 2 10.3 0.3 36x 7.6 10.3 0.2 a b 0 . 1 1 19 36 1) does not include plastic or metal protrusion of 0.15 max. per side 2) does not include dambar protrusion of 0.102 max. 1) 2) pin 1 bottom view 9 4.2 - 0 . 0 0 0.25 gauge plane 0.35 x 45 (1.8) die pad exposed index marking pin 1 18 1 19 36 for further info rmation on alternative pa ckages, please visit our website: http://www.infineon.com/packages . dimensions in mm
data sheet 27 rev. 1.0 2016-09-29 TLE9202ED dual 6 a h-bridge with spi revision history 8 revision history revision date changes 0.1 2015-03-04 initial target data sheet 0.2 2015-06-25 chapter 1 : updated pin assignment 0.3 2016-08-25 editorial changes chapter 7 : package outlines 1.0 2016-09-29 editorial changes chapter 4.3 p_5.3.1 p_5.3.2 chapter 5 p_6.0.1 p_6.0.43 p_6.0.51
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